2. INTRODUCTION
With the conventional numeric approach the synthesis of high frequency
modulated signal is based on a DSP microcontroller which generates an intermediate
signal, usually with a very low (or null) carrier frequency, and on a up
converter, either analog or digital, which shifts the signal to the desired
output frequency. My first allmode digital HF transmitter (1991)
was based on this architecture and used a Motorola DSP56001 together with
the famous Analog Devices AD7008 direct digital synthesizer [1].
In the last years reconfigurable logic circuits have made possible
the integration of more and more complex functions into a single integrated
circuit, leading to small and cheap "Systems on Chip". Following the SoC
approach, I developed a compact digital SSB exciter which fits into a small
(30,000 gates) Xilinx FPGA, the XC2S30. The logic core includes all the
functions required to transform a audio input signal into a 36 MSPS, 9
MHz SSB signal which is converted back in the analog domain by a 14bit
DAC, an AD9754 (or by a cheaper, pin to pin equivalent, 10bit DAC AD9760).
The core integrates a 12 KSPS 10bit sigmadelta audio ADC and a 14bit
numeric version of the classical Weaver modulator. Using serial arithmetic
circuits and efficient frequency conversion/filtering algorithms, it has
been possible to contain the core area to four hundred slices and three,
4,096bits, RAM Blocks (approx. 90% of the slices and 50% of the Block
RAM available in a XC2S30 FPGA).
3. DIGITAL SYNTHESIS OF A SINGLE SIDE BAND SIGNAL
3.1. The Weaver Modulator
The block diagram of an analog Weaver modulator [2]
is shown in fig.1. The input signal spectrum is converted to a zero i.f.
band pass signal by means of a quadrature frequency converter and a low
frequency oscillator. The zero i.f. signal is then filtered by two
identical low pass filters which suppress the unwanted sideband and converted
to the final frequency by a second high frequency quadrature upconverter.
Fig.1 – The Weaver modulator
Fig.2 shows the processing steps operated on the spectrum of an audio
input signal to obtain the desired IF SSB output. For a radio communication
system it is widely accepted to limit the input audio bandwidth to 2400
Hz (from 300 to 2700 Hz). The audio input is a pass band signal with a
1500 Hz center frequency.
With the first mixing one of the two side bands of the input signal
is converted to a zero carrier frequency signal (usually called by engineers
a complex low pass signal, or zero i.f. signal). To obtain such a zero
i.f. signal, the frequency f1 of the l.f. quadrature oscillator should
equal that of the input signal, that's to say 1500 Hz.
The other sideband is moved (in absolute) to an higher frequency. It
is up to the two low pass filters to reject it, while passing unaltered
the zero i.f. sideband to the next conversion stage. The low pass filters
should exhibit a low attenuation and ripple in the band 1200/1200 Hz (wanted
sideband) and introduce a large attenuation for frequencies, in absolute,
greater than 1800 Hz (unwanted sideband).
The second quadrature mixer converts the zero IF single sideband signal
to the desired IF frequency f2. Fig.2 shows the generation of an USB signal.
It is sufficient to invert the sign of one of the quadrature oscillator
outputs to obtain a spectral inversion and the generation of an LSB signal.
Note that the suppression of the carrier is due to the action of the
first two mixers, which are supposed to be perfectly balanced, and to the
assumption that the input signal has no DC component.
Fig. 2  SSB signal generation with the Weaver modulator.
3.2. The Digital Version
From the point of view of the center frequency of the processed signals,
we can divide a SSB Weaver modulator with i.f. or r.f. output in two sections.
The first one is an audio section which processes a low frequency input
signal and is made by the first frequency converter with its 1500 Hz quadrature
oscillator and the two low pass filters. The second one is an high frequency
section and is formed essentially by an high frequency quadrature up converter.
A numerical implementation of the modulator shall take in account the different
processing needs of the audio and the h.f. sections.
In a real time DSP circuit, the complexity is proportional to the number
of arithmetic operations per second required to perform the desired task.
Since the number of operations per second is the product of the number
of operations required per sample times the sampling frequency, it is important
both to reduce the number of operations/sample and minimize the sampling
frequency. The reduction of the number of operations/sample is accomplished
with the choice of the right algortihm. The analysis and the simulation
of a particular DSP algorithm help to do the right balance between the
circuit performance, which depends upon the algorithm itself and the calculus
precision, and the required logic resources. But if we fail to reduce the
sampling frequency to the minimum value which allows easy transformations
of signals between the analog and the digital domains, we are wasting processing
resources by sure.
In a SSB Weaver modulator the input signal has a bandwidth of roughly
3 KHz and can be sampled at some ten kilohertz rate. The output is a h.f.
signal instead and requires a much higher sampling rate, usually not less
than three times the maximum output carrier frequency. A numerical version
of the modulator is shown in fig. 3. It can be noted that two circuits
named "interpolators" are inserted between the leftmost l.f. section of
the modulator, sampled at an audio rate, and the r.f. section (rightmost)
which is sampled at a very high frequency. The function of the interpolators
is then that of sample rate conversion, from a low value to an higher one.
Fig. 3 – Block diagram of the digital SSB Weaver modulator
The quality of a digitally synthesized SSB signal can be characterized
by the same parameters used in analog modulators:
linearity and the in band (narrow band) SNR of the modulated signal,
unwanted sideband rejection, carrier suppression and wide band spectral
purity.
In band SNR depends upon the input sampling frequency, the audio AD
converter precision and the quality of the l.f. frequency converter. Carrier
suppression and unwanted side band rejection depend upon the offset of
the AD converter and the frequency response of the low pass filters. The
wide band spectral purity of the r.f. output depends upon the interpolators,
the h.f. frequency converter, the output DA converter and output sampling
frequency.
In this modulator the precision, that's to say the width of the signal
buses, has been kept as large as possible.
In the audio section, sampled at 12 KSPS, the 1500 Hz down converter
has a 16 bit precision. The MAC units used in the low pass FIR filters
have 16 bit operands (data and coefficients) and 22 bit outputs, which
are then truncated to 16 bit before reaching the interpolators.
In the high sampling rate section, each interpolator produce a 14 bit
quantized output. Since each of them is a cascade of CIC filters, which
essentially compute a moving average of its input, a larger precision (up
to 28 bits) is required for the intermediate results before truncation.
The sampling rate of the zero i.f. ssb signal is incremented in three stages,
from 12 KSPS to 180 KSPS by a 4th order, 32 bit, x15 serial interpolator,
from 180 KSPS to 4.5 MSPS by a 2nd order, 16 bit, x25 parallel interpolator
and from 4.5 MSPS to 36 MSPS by a 1st order, x8 parallel interpolator (which
is simply a 14 bit hold register).
The 36 MSPS zero i.f. ssb signal is finally converted to a 9 MHz i.f.
signal by a simple 14 bit Fs/4 up/down converter.
4. IMPLEMENTATION ON FPGA
4.1. Architecture of a SpartanII FPGA
In Xilinx's SpartanII FPGAs, each cell (CLB, or Cell Logic Block)
is made by two "slices". As shown in fig. 4, each slice contains two FlipFlops,
two lookup tables which can synthesize any combinatorial boolean function
with 4 inputs, and carry chain logic dedicated to arithmetic functions.
Internal propagation times are in the nanosecond order of magnitude and
the maximum toggle frequency in good pipelined designs can be much higher
than 100 MHz.
Fig. 4 – Block diagram of a SpartanII slice
The device XC2S30 contains an array of 12 x 18 CLBs (fig. 5), that's
to say 432 slices (864 FlipFlops) and is equipped with 6 blocks of 4,096
bit synchronous dualported RAM. Half of these RAM blocks have been used
to store the samples and the coefficients of the modulator low pass FIR
filters.
Fig. 5 – The array 12 x 18 CLB of a SpartanII XC2S30
4.2. Sampling and AD conversion of the audio input.
The audio input is sampled at 12 KSPS with a 10 bit sigmadelta AD
converter. The converter has been realized with an operational amplifier
which integrates the error between the input signal and its 1bit quantized
replica, and compare the error versus a fixed threshold, generating a pulse
train which drives the AD converter logic. The pulse train is sampled at
6 MSPS, feedback to the operational amplifier and decimated to 12
KSPS by a cascade of two 1st order x25 decimators which produce a 10 bit
digital version of the input signal.
4.3. Frequency conversion of the digital audio.
The quadrature 1500 Hz down converter has been implemented with a CORDIC
algorithm [3]. The COordinate Rotation
Digital Calculator, ideated by J. Volder in 1956 [4][5],
solves the problem of coordinate rotations with simple add/subtract/shift
operations and, since a frequency conversion is just a rotation of a vector
on a plane, is the preferred way to realize frequency converters in the
hardware. In the CORDIC an arbitrary rotation of the input vector is obtained
iteratively and by successive approximations of the rotation angle.
The general formulas that transform the coordinates of a vector (x,y)
rotated by an angle phi into the new coordinates (x',y'):
x’ = cos(phi) x  sin(phi) y
= cos(phi) ( x – tan(phi) y),
y’ = cos(phi) y + sin(phi) x
= cos(phi) ( y + tan(phi) x)
may in fact be simplified if the rotation angle is such that tan(phi)
= ±2^{i}. In this case, omitting the multiplicative term
cos(phi) which is constant and indipendent upon the rotation direction,
the formulas become:
x’ = ( x  ±2^{i} y),
y’ = ( y + ±2^{i} x)
and require only add, subtract and shift operations. An arbitrary rotation
is then obtained by decomposition of the angle into a finite sum of angles
whose values satisfy the rule tan(phi) = ±2^{i} and applying
the above formulas iteratively.
The 1500 Hz frequency conversion of an audio signal sampled at 12 KHz
is just a sequential and periodic rotation of the input audio signal by
an angle of 1500/1200 · 360º = 45º.
In this ssb modulator, the frequency converter rotates the audio signal
by a fixed angle phi = 22.5º by means of a 16 bit, 5 stages, serial
CORDIC and uses the symmetry of the rotation sequence to produce the desired
output signal, as shown in Fig. 6.
Fig. 6 – 1500 Hz Digital down conversion of the audio signal
The desired 22.5º rotation is approximated by the five term sum:
atan(2^{1})  atan(2^{4})
 atan(2^{7})  atan(2^{10}) + atan(2^{12})
= 22.499138...º,
with a very good accuracy and an high spectral purity, obtained in just
80 clock cycles/sample (16 cycles per stage) and a small fraction of logic
resources which would be required to realize the same down converter with
the classic multiplier/quadrature direct digital synthesis architecture.
4.4 Low pass filtering. Unwanted sideband rejection.
In the SSB Weaver modulator the suppression of the unwanted sideband
equals the stop band attenuation of the low pass filters. To obtain a 50/60
dB rejection over a bandwidth which is about one fourth of the sampling
frequency with a linear phase flat response in the pass band, FIR filters
with at least 50 taps are required. Since the audio sampling frequency
is a small fraction of the clock frequency there are a lot of clock cycles
available to compute the filter output (in this modulator, 36 MHz/12 KSPS
= 3000 clock cycles per sample) and the arithmetic operations required
by the filters can be serialized in order to largely reduce the CLB
requirements. DSP microcontrollers rely on one or more MAC units which
execute in a single clock cycle and allow to compute the response of a
FIR filter in as many clock cycles as the filter taps. To reject adequately
the unwanted sideband we need just a fraction of such a computational speed.
Each low pass filter has to compute 50 MACs at 12 KSPS, that's to say 600,000
MAC/s and a single cycle MAC unit is not required. Using a 36 MHz clock,
there are 36,000,000 Hz / 600,000 MAC/s = 60 clock cycles available to
compute (serially) a MAC. The FIR filters I developed use 16 x 16 bit input
serial multipliers which execute in 16 clock cycles.
With a 36 MHz clock and a 12 KSPS processing rate the upper limit to
the tap number of the filters is 185, almost four time the real requirements.
I exploited this capacity to implement two 127 taps, 16 bit coefficients,
symmetric Remez FIR filter with a 0.2 dB ripple in the pass band [0, 1200
Hz] and a 80 dB stop band [1500, 6000 Hz] attenuation. They not only
reject the unwanted sideband but also the carrier which falls exactly at
the lower limit of the stop band. The frequency response of the filters
is shown in fig. 7.
Fig. 7 – Frequency response of the sideband rejecton filter
4.5. Interpolation to 36 MSPS
The spectrum of a sampled signal is periodic with period equal to the
sampling frequency. The single sideband signal generated by the audio section
of the Weaver modulator is sampled at 12 KSPS and its spectrum contains
aliased images spaced 12 KHz. The interpolators have to resample the input
signals at 36 MSPS and attenuate the unwanted images to an acceptable level.
This result is obtained with filters which introduce a large attenuation
at multiples of the input sampling frequency, as shown in the example of
fig. 8.
Fig. 8 – Interpolation of a sampled signal
A class of filters which is very efficient to the hardware implementation
of interpolators (or decimators, if the sampling rate has to be lowered)
is that of the CIC (Cascaded Integrator Comb) filters, due to E.B. Hogenauer
[6]. Fig. 9 shows the schematic diagram
of a decimator and an interpolator realized with CIC filters.
Fig. 9 – Schematic diagram of Nth order CIC decimators and interpolators
The frequency response of a CIC filter of order N, interpolation factor
R and output sample frequency fso is:
The transfer function has Nth order transmission zeros at frequencies
multiple of the input sampling frequency fsi = fso/R. The zeros are centred
on the images and attenuate them considerably.
The interpolators used in the SSB modulator resample the l.f. signal
by a factor R=3000 and attenuates the images by more than 70 dB. They are
implemented with a cascade of three interpolating stages.
The first stage includes a 4th order x15 serial CIC filter with 16
bit input (R=4, N=15) and resample the input signal at 180 KSPS. Since
its DC gain is R^{N1} = 3375, it requires log2(3375) = 12 extra
bits to avoid output overflow, leading to a 28 bit result which is truncated
to 16 bits before entering the second stage. The second stage is a 16 bit,
2nd order, x25 parallel interpolator (N=2, R=25) and resample the output
of the first stage to 4.5 MSPS. The third and last stage is a 14 bit, 1st
order, x8 interpolator (N=1, R=8) and, since it has a rectangular impulse
response, it doesn't consume any logic resource (it is just the accumulator
register of the second stage).
4.6. Up conversion to 9 MHz.
A tuneable, high sample rate, frequency converter consumes a lot of
logic. The CORDIC algorithm simplifies the conversion process but in the
generation of h.f. signals it has to be necessarily implemented in
parallel form. Each CORDIC stages requires two adders/subtracters for the
rotation of the input vector and a third adder/subtracter for the calculus
of the residual angle which feeds the next stages. For adequate spectral
purity in transmission chains, the converter can require 16 cascaded stages
with 16 bits buses for the input complex vector and for the rotation angle.
A pipelined version of such a converter would use 48 adders/subtracters
with registered output, for a total of 768 FlipFlops, that's to say almost
all the logic of a XC2S30 device.
Anyway, if tuning is not required and the output frequency is limited
to exactly one fourth of the sampling frequency, the converter can be realized
with a much less logic circuits.This is the reason a 36 MSPS sample frequency
has been chosen in this modulator. In fact in a digital frequency converter
with Fs/4 output frequency, the input signal vector has to be rotated sequentially
by angles which are multiples of 90º. This operation translates
in a four cycle periodic and sequential exchange and twocomplement of
the input vector components, as shown in fig. 10.
Fig. 10 – A fast Fs/4 frequency converter
On a Xc2S30 a 14 bit Fs/4 updown parallel frequency converter fits
into 8 slices (16 FFs) and runs at almost 200 MSPS.
5. CIRCUIT DESCRIPTION
The schematic diagram of the SSB modulator is shown here.
The modulator requires a stabilized +5 Vdc power supply, provided at pin
10 of the JP3 connector.
The input audio signal (pin 1 of JP3) is filtered and amplified by
the operational amplifier IC2A. The input signal level required to drive
the modulator is about 100 mVpp. The antiparallel couple of diodes BAV99
(D4) limits the gain of the preamplifier and avoid the saturation of the
next stages. The section IC2B of the OPA2340UA opamp works as the integrator/comparator
section of the audio AD converter as explained in the paragraph 4.2. The
inputs PTT\, BFO\, SSB/CW\, USB/LSB\ and TWOTONE\ available at connector
JP3 control the operational mode of the modulator. PTT\ enables the audio
input, BFO\ enables the generation of the beat signal for the receiver
product detector, SSB/CW\ select the corresponding modulation, USB/LSB\
selects the transmitted side band, KEY\ is the CW key input, and
TWOTONE\ enables the internal two tone generator. All the input interface
signals available on JP3 are active low and should be driven by open collector
sources or switches connected to ground.
The programmable gate array IC3 (an XC2S305VQ100C) processes the audio
signal and the CW key input to generate a digital, 14bit, 9 MHz
ssb output signal which is converted in the analog domain by the DA converter
IC4 (an AD9754, or a cheaper pintopin compatible 10 bit AD9760 converter)
and filtered by the antialias filters formed by L2L6 and C32C38. The
modulator has two outputs, TXOUT and BFOOUT, available at connector JP4.
The p.e.p. output level is 11 dBm p.e.p. (approx. 90 mVp on a 50
ohm termination).
IC1 is a 512 KBit serial EEPROM which stores the FPGA configuration
bitstream. The bitstream is uploaded in a fraction of second when the the
power supply is applied to the SSB modulator. The LED D3 lights when the
configuration phase is in progress and is off during normal operations.
In system programming of the EEPROM allows to easily upgrade the modulator
core and is accessible via the connector JP1, which accepts Atmel's standard
programming cable and software.
At the connector JP2 are available the signals of the JTAG port of
IC2. By means of this port it is possible to reprogram the FPGA with Xilinx
software development toolkit and upload new core versions, overriding the
EEPROM.
The 36 MHz crystal oscillator QG1 is the main clock source for the
modulator core and the transmission DAC IC4.
The voltage regulator IC5 and the bipolar transistor Q1 provides the
+3.3V and the +2.5V stabilized voltages required to drive IC1, IC2, IC3
and IC4. The modulator sinks 140 mA at pin 10 of JP3 where the stabilized
+5Vdc power supply is applied. It is necessary that the external power
supply is equipped with a large capacity electrolytic capacitor (at least
2,200 uF) or that, alternatively, it is able to provide a 500 mA peak current.
This peak current is required by some milliseconds by the XC2S30 i.c. when
it is powered up. The network formed by C18R20 delays the internal +2.5V
power supply for a short fraction of second allowing the charge of the
external electrolytic capacitor which provides the extra current in the
case that the external power supply peak current is less than 500 mA.
6. EXPERIMENTAL RESULTS
Fig. 11 shows a photo of the first sample of the digital SSB modulator.
Fig.12 and fig.13 shown the unwanted sideband rejection, measured with
a 1 KHz input signal, and wide band spurious responses (117 MHz). The
measures have been carried with a HP8563E spectrum analyzer. As shown by
fig.12 the unwanted side band rejection is better than 80 dB. The quantization
noise of the sigma delta AD converter is evident, it is confined in the
bandwidth of the the selected side band and its amplitude is quite low.
In fig. 13 it is visible the highest spurious response generated by the
modulator. Its amplitude is 75 dB lower than the p.e.p. output power. In
the tests performed it has been verified also the spectral purity of a
modulator in which the 14 bit DA converter AD9754 was substituted by a
cheaper 10 bit DA converter (AD9760). The SFDR measured in this case was
only slightly worse. The prototype with the 10 bit DAC showed just a greater
noise floor, and still very low for amateur applications, in a bandwidth
of a couple of megahertz around the centre frequency.
Fig.11 – A photo of the digital SSB modulator


7. CONCLUSIONS
Exploiting DSP algorithms optimised for the implementation on the hardware
of arithmetic and trigonometric functions, a compact digital SSB modulator
has been developed. The modulator can be used as the exciter of homebrew
SSB/CW transmitters and the BFO of the receiver chain.
The logic core of the modulator was developed in VHDL language making
large use of serial arithmetic modules. It fits into a cheap 30 Kgate
FPGA (see fig. 14) and surpasses the performance of classic analog SSB
modulators. In future developments the digital SSB modulator and a CORDIC
tuneable up converter will be integrated in a single gate array to realize
a direct synthesis 030 MHz digital SSB/CW transmitter.
Fig. 14 – The core of the SSB modulator in a XC2S30 device
8. REFERENCES
[1] F. Nardone, “Il Personal computer come una radio”,
Quotidiano “Il Messaggero Veneto”, 22 Maggio 1992.
[2] Donald K. Weaver, “A Third Method of Generation
and Detection of SingleSideband Signals”, IRE Proceedings, 1956, pp. 17031705.
[3] Ray Andraka, “A survey of CORDIC algorithms
for FPGA based computers”, ACM, Monterey, 1998 (disponibile anche su Internet
http://www.andraka.com/files/crdcsrvy.pdf )
[4] J. Volder, “Binary computation algorithms for
coordinate rotation and function generation”, Convair Report IAR1 148
Aeroelectrics Group, June 1956.
[5] J. Volder, “The CORDIC Computing Technique”,
IRE Trans. on Computers, v. EC8, Sept. 1959, pp. 330334
[6] E.B. Hogenhauer, “An economical class
of digital filters for decimation and interpolation”, IEEE Trans. on Acustics,
Speech and Signal Processing, ASSP29(2), 1981, pp. 155162.